ABSTRACT
Metal-oxide semiconductor (MOS) transistor behavior has already been demonstrated at the research level, down to a 6-nm gate length on fully depleted silicon on insulator (SOI) [1]. As complementary metal oxide semiconductor (CMOS) technologies continue to shrink, however, new physical phenomena are becoming increasingly important in the device behavior, setting up new challenges especially for lowpower design. Some authors are even suggesting that power consumption will set the limits of scaling on an application dependent way [2]. Compared to traditional CMOS bulk technologies, SOI technologies are foreseen as alternative technologies that could lead to a better trade-off between active and leakage power. After a brief overview of the various scenarios proposed by the International Technology Roadmap for Semiconductors (ITRS) [3], the four main causes of limitations are discussed:
1. Voltage limits and subthreshold leakage 2. Tunneling currents
3. Statistical dispersions 4. Poly depletion and quantum effects
In addition, for each of those limitations, design challenges and proposed solutions are briefly presented, for bulk and SOI technologies. Finally, new innovative transistor architectures and technologies are described, and their relevance regarding the previous problems discussed.
