ABSTRACT
This book has explored techniques that minimize interprocessor communication and synchronization costs in statically scheduled multiprocessors for DSP. The main underlying theme is that communication and synchronization in statically scheduled hardware is fairly predictable, and this predictability can be exploited to achieve our aims of low overhead parallel implementation at low hardware cost. The first technique described was the ordered transactions strategy, where the idea is to predict the order of processor accesses to shared resources and enforce this order at run-time. An application of this idea to a shared bus multiprocessor was described, where the sequence of accesses to shared memory is predetermined at compile time and enforced at run-time by a controller implemented in hardware. A prototype of this architecture, called the ordered memory access architecture, demonstrates how low overhead IPC can be achieved at low hardware cost for the class of DSP applications that can be specified as SDF graphs, provided good compile time estimates of execution times exist. We also introduced the IPC graph model for modeling self-timed schedules. This model was used to show that we can determine a particular transaction order such that enforcing this order at run time does not sacrifice performance when actual execution times of tasks are close to their compile time estimates. When actual running times differ from the compile time estimates, the computation performed is still correct, but the performance (throughput) may be affected. We described how to quantify such effects of run time variations in execution times on the throughput of a given schedule.
