ABSTRACT
The basis of dc design, definition of logic levels, noise margin, and transfer characteristics were discussed in Chapter 71 using a DCFL and SCFL inverter as examples. In addition, methods for analysis of highspeed performance of logic circuits were presented. These techniques can be further applied to the design of GaAs MESFET, HEMT, or P-HEMT logic circuits with depletion-mode, enhancement-mode, or mixed E/D FETs. Several circuit topologies have been used for GaAs MESFETs, like direct-coupled FET logic
(DCFL), source-coupled FET logic (SCFL), as well as dynamic logic families,
and have been extended for use with heterostructure FETs. Depending on the design requirements, whether it be high speed or low power, the designer can adjust the power-delay product by choosing the appropriate device technology and circuit topology, and making the correct design tradeoffs.
