ABSTRACT
The use of bare die in chip on board (COB) and multichip module (MCM) applications is increasing, with designers looking for end item size and weight reduction (automotive applications have bond wires going directly from the die to a connector). The use of bare die eliminates the timing delays (caused by stray inductance and capacitance) associated with the leadframes and device input/outputs (I/Os). For burst mode static RAMs, 0.5 to 2 ns or a 20% improvement in access time is achieved with bare die product. Using bare die is not without problems, including testing issues and cost. At this time, it is more costly for vendors to handle and ship bare die than packaged devices. Using bare parts makes it important to use known good die (KGD); otherwise, the final assembly has to be scrapped as the device cannot be removed. Industry standards on bare die testing are still evolving. Small portable devices can also use flip chip bonding to a circuit. Current technology bonding machines can bond 1C chips with 1 x 10* bumps of 1-um size, with a 30-um pitch. 1C packaging can be divided into the following categories:
• Surface mount packages (plastic or ceramic) • Chip-scale packaging • Bare die • Through-hole packages • Module assemblies
"Portions of this chapter were adapted from Meeldijk, V., 1995. Electronic Components: Selection and Application Guidelines, Chap. 12, Wiley-Interscience, New York, with permission.
