ABSTRACT
Once we have understood the basic features of a very-large-scale integration (VLSI) cell, datapath subsystems, and memory subsystems design, we are now in a position to understand the important system-level design issues. These issues include the logic module, interconnect network, power distribution network, clock generation and distribution network, input/output (I/O) module, and electrostatic discharge (ESD) protection network. The power management has been explored in Chapter 6. The important related design issues at the system level include signal integrity, clock integrity, and power integrity.
