ABSTRACT
Ferroelectric nonvolatile memories are attractive as replacements for conventional EEPROM and flash EEPROM because of lower write voltages, faster write speeds, and potentially fewer processing steps. Successful commercial development requires the integration of ferroelectric capacitors with the well-established and highly-developed Si-based CMOS technology. However, the integration of PZT ferroelectric capacitors into a Si-based CMOS technology results in a number of materials interactions. Not only do the components of the capacitors interact with each other, but also the capacitor materials can interact with the usual CMOS materials. Further, a number of common CMOS processes that are desired to follow capacitor formation frequently result in degradation of ferroelectric properties. Because of the temperatures used in crystallization of PZT, the usual integration schemes place the ferroelectric capacitors over a dielectric layer covering the completed transistors and below the metal and interlevel dielectric layers used to form the chip interconnect. A schematic cross-section is shown in Fig. 1 for a typical integration scheme. In this paper we discuss some of the materials interaction hurdles that must be resolved in developing a ferroelectric technology.
