ABSTRACT
There is a strong trend towards integrating FPGA with various heterogeneous hardware components, such as RISC processors, embedded multipliers and memory blocks (e.g., Block RAMs in Xilinx FPGAs). Such integration leads to a reconfigurable System-on-Chip (SoC) platform, an attractive choice for implementing many embedded systems. FPGA based soft processors, which are RISC processors realized using the configurable resources available on FPGA devices, are also becoming popular. Examples of such processors include Nios from Altera [3] and MicroBlaze and PicoBlaze from Xilinx [97]. One advantage of designing using soft processors is that they provide new design trade-offs by time sharing the limited hardware resources (e.g., configurable logic blocks on Xilinx FPGAs) available on the devices. Many control and management functionalities as well as computations with tightly coupled data dependency between computation steps (e.g., many recursive algorithms such as Levinson Durbin algorithm [42]) are inherently more suitable for software implementations on processors than the corresponding customized (parallel) hardware implementations. Their software implementations are more compact and require a much smaller amount of hardware resources. Such compact designs using soft processors can effectively reduce the static energy dissipation of the complete system by fitting into smaller FPGA devices [93]. Most importantly, soft processors are “configurable” by allowing the customization of the instruction set and/or the attachment of customized hardware peripherals in order to speed up the computation of algorithms with a large degree of parallelism and/or to efficiently perform some auxiliary management functionalities as described in this chapter. The Nios processor allows users to customize up to five instructions. The MicroBlaze processor supports various dedicated communication interfaces for attaching customized hardware peripherals to it.
