ABSTRACT
Since the introduction of Field-Programmable Gate Arrays (FPGAs) in 1984, the popularity of reconfigurable computing has been growing rapidly over the years. Reconfigurable hardware devices with multi-million gates of configurable logic have become available in recent years. Pre-compiled heterogeneous hardware components are integrated into reconfigurable hardware, which offer extraordinary computation capabilities. To improve design flexibilty and ease-of-use, modern FPGA devices may contain on-chip configurable processor subsystems. These processor subsystems provide great design flexibilities similar to general-purpose processors and programmable DSP (Digital Signal Processing) processors while allowing application optimization. Reconfigurable hardware offers many unique advantages compared with traditional ASICs (Application-Specific Integrated Circuits). The advantages of application development using reconfigurable hardware are discussed in detail in the following sections. • Reduced development tool costs Designs using FPGAs can greatly reduce the development tool costs com-
pared with application specific ICs [12]. For ASIC based application development, the average seat of development tools costs around $200,000 per engineer. In addition, engineers have to go through a lengthy low-level design process. The low-level design process includes HDL (Hardware Description Language) based register transfer level (RT level) design description, functional and architectural simulation, synthesis, timing analysis, test insertion, place-and-route, design verification, floorplanning, and design-rule checking (DRC). Due to the complicated development process, ASIC engineers often need to use the tools from multiple EDA (Electronic Design Automation) vendors, which dramatically increases the costs for development tools. In comparison, for FPGA based application development, the average seat of development tools costs between $2,000 and $3,000, which is much lower than the cost for ASIC development tools. The FPGA based application development goes through a similar process as that of ASIC such as synthesis, functional and architectural simulation, timing analysis, place-and-route, etc. However, due to the reconfigurability of FPGA devices, their design insertion and de-
FIGURE 1.1: Non-recurring engineering costs of EasyPath
sign verification are much simpler than ASICs. For example, users can use hardware co-simulation to simulate and verify the designs under test. Due to the relatively simpler development process, there are usually adequate tools provided by FPGA vendors at a very low costs. Many value-added tools from EDA vendors are also available for prices ranging from $20,000-$30,000. • No non-recurring engineering costs Non-recurring engineering (NRE) costs refer to the costs for creating a new
product paid up front during a development cycle. The NRE costs are in contrast with “production costs”, which are ongoing and are based on the quantity of material produced. For example, in the semiconductor industry, the NRE costs are the costs for developing circuit designs and photo-masks while the production costs are the costs for manufacturing each wafer.
