The LUT itself is a small 16×1-bit RAM with contents preloaded at the con‹guration stage. Clearly, any combinational logic with four input signals can be implemented, which is the primary reason for the ¨exibility of the FPGA devices. But when more than four signals participate in the logic function, more layers of LUT are normally necessary. For example, if we need a 7-input AND gate, it can be implemented with two cascaded lookup tables.