ABSTRACT
A circuit for the clock signal generation or recovery is often required to achieve accurate data transfer between the different building blocks of very large-scale integrated-circuits operating at high speed. To keep negligible the charge leakage, the duration of the sampling phase and hold phase required in the operation of switched-capacitor circuits is controlled by non overlapping clock signals. A phase detector (PD) circuit, which can exhibit either a linear or binary transfer characteristic, is required for the generation of the phase error signal. The aforementioned PD architecture samples the input data at the rising and falling edges of the in-phase clock, while the quadrature clock is used to track the data transition. A charge-pump circuit is required to convert the logic pulses generated by the phase and frequency detector or PD into current signals that are used to drive the loop filter providing the voltage-controlled oscillator control voltage.
