ABSTRACT
In three-dimensional (3D) integration based on die-to-wafer stacking, high-precision chip alignment and low-temperature chip bonding are major two key technologies. However, traditional robotic pick-and-place chip assembly for the die-to-wafer 3D integration has a great disadvantage in production throughput due to the sequential one-by-one process. To overcome the issue, a new multichip self-assembly technology using liquid surface tension as a driving force has been proposed. In the advanced die-to-wafer 3D integration using the self-assembly technology, by the surface tension of liquid droplets, a large number of known good dies (KGDs) with/without through-Si vias (TSVs) can be simultaneously, quickly, and precisely aligned to pre-determined areas photolithographically formed on Si wafers, and consequently, the self-assembled KGDs can be tightly bonded to the wafers at room temperature. Here, an overview of the self-assembly technology for the advanced die-to-wafer 3D integration using the self-assembly technology is introduced and the potential applications of the self-assembly-based 3D integration are described.
8.1 INTRODUCTION-WHY SELF-ASSEMBLY IS REQUIRED?In the past few years, development of three-dimensionally stacked integrated circuits (3D ICs) has increasingly activated towards a technological breakthrough overcoming limitations in downscaling electron devices by Moore’s law. The most striking feature of the 3D ICs is that a huge number of very short TSVs with a length of several tens microns can vertically connect multiple stacked thin chips, as shown in Figure 8.1. Therefore, the 3D integration technologies can not only miniaturize the chip size and reduce the length of long global wirings used in system on a chip (SoC) and long bonding wires used in system in packaging (SiP), but also significantly increase the signal processing speed and decrease the power consumption.1-3In addition to the TSV formation, several key technologies are required for the 3D IC fabrication: microbump formation, chip/wafer thinning, adhesive injection (unique underfilling under vacuum4), and chip/wafer alignment and bonding. As shown in Figure 8.2, these key technologies can provide vertically stacked thin wafers (or chips) in which TSVs with 30 mm in length and metal microbumps with 5 mm in width can electrically connect between upper and lower wafers (or chips).
