ABSTRACT
Through Silicon Via (TSV) Etching is a key process fabrication module employed in 3D IC technologies. While there are yet to be significant volumes of commercially available TSV-based packaged devices in silicon IC technologies today, there are scores of TSV development activities currently underway within programs organized by semiconductor capital equipment consortia, university research centers, Integrated Devices Manufacturers, packaging houses, and various national and international government-sponsored efforts. Many 3D technology topics require substantial new progress be made on difficult areas of process technology, for example low-temperature deposition of dielectric films in silicon vias for Via-Last fabrication schemes, TSV etching, however, benefits greatly from the large body of knowledge readily available from two important sources. For deep etching of features and structures in silicon, the plasma etch processes developed for Microelectromechanical (MEMS) device fabrication can be readily ported over to the TSV etch module for 3D technology platforms. And, for a general understanding of High Volume Manufacturing (HVM) requirements and challenges for through-wafer processing technologies, the Compound Semiconductor industry has routinely and successfully employed backside via structures for many years. This chapter reviews the work already performed in TSV etching by the Compound Semiconductor industry, then examines deep reactive ion etching (DRIE) processes as developed for MEMS device fabrication. Following this review, the chapter presents an analysis 3D Integration for VLSI Systems Edited by Chuan Seng Tan, Kuan-Neng Chen and Steven J. Koester Copyright © 2012 by Pan Stanford Publishing Pte. Ltd. www.panstanford.com
of the specific requirements of TSV etching for silicon device 3D technology, and then concludes with a look forward to TSV etching requirements visible on the near-term horizon. 4.1 THROUGH WAFER VIA ETCHING IN COMPOUND
Here is a familiar sequence of processing steps: • A wafer is attached backside-up to a carrier substrate using a high temperature thermal-plastic adhesive and a vacuum bonding machine. • Wafer thickness measurements are collected on the bonded wafer and
the wafer then undergoes a mechanical thinning process followed by a chemical polish to remove any grind damage to the backside surface.
