ABSTRACT
Radio-frequency (RF) frequency synthesis is a special case of the clock generation. The input to the frequency synthesizer is a fixed reference frequency of a crystal that exhibits extremely low phase noise. Phase-Locked Loop (PLL) is to generate a local clock phase-locked to the input clock, and the low-jitter or low phase noise clock generation is the most basic function of PLL. Low-frequency digital PLLs have numerical voltage-controlled oscillator (VCO) and digital phase detector (PD), but in the recent high-speed clock recovery for disk drive and networking, high-speed digital data are directly sampled and processed in parallel. However, in the latter case, the PD should be a time-to-digital converter, and the loop filter should be a digital filter because the synthesizer VCO takes only the digital input modulus. The wideband charge-pump PLL is now used as a low-jitter VCO that is digitally controllable.
