ABSTRACT
Low cost per bit and high packing density of dynamic random access memories (DRAM) are unmatched by any other semiconductor memory. The initial-stage cell was a simpler entity, of course, in comparison to the complex products, in the form of a single access transistor and a storage capacitor laid side by side in two dimensions; it has been called a planar DRAM cell. During DRAM development stages two important figures of merit for a DRAM cell were/are given due importance. The chapter describes a DRAM cell in which both the vertical transistor and storage capacitor are realized in a trench and discusses stacked capacitor cell basics and some variations. To maintain required capacitance for higher-density DRAM, the trench needs to be made deeper in Corrugated Capacitor Cell, giving rise to the leakage problem via punch-through between neighboring trenches, in addition to the practical problem of etching a deeper trench and suffering from high soft error rate.
