ABSTRACT
This chapter discusses the ways in which the challenges that arose in designing low-voltage/low-power Dynamic Random Access Memory (DRAM) were faced and the problems resolved especially with regard to power dissipation. Continued reduction of minimum feature size and the advancements in the fabrication processes were the main reasons for the DRAM density enhancement. As soon as multi-megabit DRAM appeared on the horizon, it opened completely new application areas for the DRAMs. A DRAM chip can broadly comprise the memory cell array, row and column decoders, and other peripheral circuits. Irrespective of the nature of leakage currents and their weights, power has to be supplied to the DRAM, which, along with the normal chip-functioning requirement, shall also include the power dissipated due to the leakage currents. Improvement of DRAM cell retention time is a critical factor in realizing high-density DRAMs, since it needs to be doubled with every generation and chances of failure of weak cells rise.
