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# Hapter 6 High-speed Implementation Of Elliptic Curve Scalar Multiplication On Fpgas

DOI link for Hapter 6 High-speed Implementation Of Elliptic Curve Scalar Multiplication On Fpgas

Hapter 6 High-speed Implementation Of Elliptic Curve Scalar Multiplication On Fpgas book

# Hapter 6 High-speed Implementation Of Elliptic Curve Scalar Multiplication On Fpgas

DOI link for Hapter 6 High-speed Implementation Of Elliptic Curve Scalar Multiplication On Fpgas

Hapter 6 High-speed Implementation Of Elliptic Curve Scalar Multiplication On Fpgas book

## ABSTRACT

This chapter presents the construction of an elliptic curve crypto processor (ECCP) for the NIST speciﬁed curve [393] given in Equation 6.1 over the binary ﬁnite ﬁeld GF (2233).

y2 + xy = x3 + ax2 + b (6.1)

The processor implements the double and add scalar multiplication algorithm described in Algorithm 2.3. The processor (Fig. 6.1), is capable of doing the elliptic curve operations of

point addition and point doubling. Point doubling is done at every iteration of the loop in Algorithm 2.3, while point addition is done for every bit set to one in the binary expansion of the scalar input k. The output produced as a result of the scalar multiplication is the product kP . Here, P is the basepoint of the curve and is stored in the ROM in its aﬃne form. At every clock cycle, the register bank (regbank) containing dual ported registers feed the arithmetic unit (AU) through ﬁve buses (A0, A1, A2, A3, and Qin). At the end of the clock cycle, results of the computation are stored in registers through buses C0, C1 and Qout. There can be at most two results produced at every clock. Control signals (c[0] · · · c[32]) generated every clock cycle depending on the elliptic curve operation control the data ﬂow and the computation done. Details about the processor, the ﬂow of data on the buses, the computations done, etc. are elaborated on in following sections.