ABSTRACT
Mitigation...................................................................................................... 160 7.2.1 Circuit Redundancy .......................................................................... 160
7.2.1.1 Dual Redundant Approaches ............................................. 161 7.2.1.2 Dual-Interlocked Cell ........................................................ 162
7.2.2 Temporal Redundancy ...................................................................... 162 7.2.3 Combined Approaches ...................................................................... 163
7.2.3.1 DF-DICE ............................................................................ 163 7.2.3.2 Temporal DICE FF ............................................................ 165 7.2.3.3 Bistable Cross-Coupled DMR FF ...................................... 166 7.2.3.4 Filter Elements in the Latch Feedback Loop ..................... 167 7.2.3.5 Layout and Circuit Design Interactions ............................. 168
7.2.4 Delay Element Circuits ..................................................................... 171 7.2.4.1 Producing Delays with Inversions ..................................... 171 7.2.4.2 Current-Starved Delay Elements ....................................... 173 7.2.4.3 Low Gate Voltage Redundant Delay Element ................... 173
7.2.5 Taxonomy and Comparison .............................................................. 173 7.3 Design-Level Methods for Hardness Analysis ............................................. 174
7.3.1 Circuit Simulation-Level Modeling .................................................. 174 7.3.1.1 Upset Modeling .................................................................. 174
7.3.2 Mitigating MNCC ............................................................................. 177 7.3.2.1 Spatial Node Separation to Ensure MNCC Hardness ....... 178 7.3.2.2 Multiple Node Upset and Spatial Separation ..................... 178 7.3.2.3 Systematic Fault Analysis .................................................. 181
Using hardened latches is the most straightforward method to harden a logic design against soft-errors. By hardening the sequential circuits (i.e., the flip-flops [FFs] and latches) as well as hardening the memories appropriately, the rest of a digital design need not be altered. There is a significant timing impact, depending on the choice of hardened FF circuit and the level of hardness required.
