ABSTRACT
The interaction of ionizing radiation with a circuit’s semiconductor components can manifest as spurious transient signals within the circuit. A single-event transient (SET) may disrupt the valid electric signals or compromise the functionality of the circuit. SETs may result in single-event upsets (SEUs) in digital circuits if the transients alter the state of memory (e.g., a memory cell or data register can be changed from a logic 0 state to a logic 1 state or vice versa). SEUs can lead to circuit errors if corrupted data propagates throughout the circuit and is observable at the output. These upsets are often termed soft errors, as they do not result in permanent damage
9.1 Introduction .................................................................................................. 229 9.2 Reducing the Collected Charge .................................................................... 231
9.2.1 Substrate Engineering ....................................................................... 231 9.2.2 Layout-Level Mitigation ................................................................... 233
9.2.2.1 Nodal Separation and Interleaved Layout .......................... 235 9.2.2.2 Differential Design ............................................................ 236
9.3 Reducing the Critical Charge ....................................................................... 238 9.3.1 Redundancy ...................................................................................... 239 9.3.2 Averaging (Analog Redundancy) ...................................................... 241 9.3.3 Resistive Decoupling ........................................................................ 241 9.3.4 Resistor-Capacitor (RC) Filtering .....................................................244 9.3.5 Modifications in Bandwidth, Gain, Operating Speed,
and Current Drive .............................................................................245 9.3.6 Reduction of Window of Vulnerability ............................................ 247 9.3.7 Reduction of High-Impedance Nodes ..............................................248 9.3.8 Hardening via Charge Sharing .........................................................250 9.3.9 Hardening via Node Splitting ........................................................... 253
9.4 Summary ...................................................................................................... 258 References .............................................................................................................. 259
within the circuit, although they can result in application or mission failure if the soft error disrupts a critical function.
