ABSTRACT
Current computing systems based on volatile logic circuits and working memories suffer from two problems that limit the performance improvements that can be realized by semiconductor device miniaturization as shown in Figure 5.1a. One is the large power consumption in cache memories and the main memory. The other is the speed gap between the last level (LL) cache by static random access memory (SRAM) and the main memory by dynamic random access memory (DRAM) and that between the main memory and the storage memory by solid-state drive (SSD) or hard disk drive (HDD). As the length of the channel decreases, the SRAM memory cell realizes a large subthreshold leakage. This trend, together with the requirement to increase the caches’ capacity in order to boost the computer’s performance, drastically increases the caches’ power consumption, especially in the LL cache having the largest capacity. This power increase is a bottleneck in the goal to realize increased computer performance using device scaling. The DRAMs in the main memory rely on a single-ended read scheme, with their cycle time being limited to several tens of nanoseconds, which is much slower than that of the LL cache, whose cycle time is as fast as a few nanoseconds. Storage memories are also much slower than the main memories. These differences in speed are also a serious bottleneck to realizing improvements in the computer performance.
