It becomes more and more difficult to exploit the benefits of device scaling. This difficulty motivates us to develop 3D system integration. Large-scale integration (LSI) chips are three-dimensionally stacked and connected with vertical interchip links in 3D system integration. It is important to develop high-performance vertical interchip links

since the total system performance of 3D system integration deeply depends on the performance of interchip links. So far, several kinds of vertical interchip links have been developed and reported. As typical developments, microbump technology [9], through-silicon via (TSV) technology [10], a capacitive-coupling interchip link [11], and an inductive-coupling interchip link [12] have been proposed and investigated. The microbumps and TSV technology are in practical use; however, they require an additional mechanical process, which leads to high cost. On the other hand, capacitive-coupling links can be developed by a normal CMOS process and do not require an additional mechanical process. However, capacitive-coupling links have limitations in implementation. Capacitive-coupling links can be applied only in face-to-face implementation. Contrarily, inductive coupling has no limitations in implementation style. Inductive-coupling links enable communication between more than three stacked chips. Figure 11.1 shows a conceptual image of wirelessly connected 3D system integration. The data, clock, and power are delivered using inductive-coupling links. Thus, noncontact 3D system integration can be realized.