ABSTRACT
It is not difficult to imagine how this process works. The input signal needing correction is fed into a “frame synchronizer” (stand alone box or internal device process). It is written to a digital frame memory (sometimes called an elastic buffer) at the input rate and timing. Next, a separate process reads from the same memory to create a new signal for output. The output timing is aligned to the provided master reference signal. As long as the input data rate and output data are equal on average, then the buffer will not overflow or underflow. There is a clean separation of the two processes and any output H/V timing relation may be produced independent of the input signal timing.
