ABSTRACT
This chapter is devoted to exploring implementation techniques that manufacturers have adopted to achieve the goal of making their central processing units (CPUs) process information as rapidly as possible. The most ubiquitous of these techniques is known as pipelining. One of the first super pipelined processors was the MIPS R4000, which had an eight-stage pipeline instead of the four- or five-stage design. The eight stages were instruction fetch (first half), instruction fetch (second half), instruction decode and register fetch, execution, data cache access (first half), data cache access (second half), tag check, and write back. In the chapter, author examined several advanced design concepts involving internal concurrency of operations within a single CPU core. The concept of pipelining was the main focus of our attention because almost all commonly used methods for enhancing the performance of a CPU are based on pipelining and because, as a result, almost all modern microprocessors are internally pipelined to some extent.
