A single cycle low latency bypass router based on network on chip

Network on chip (NoC) due to its advance in architectural designs becomes the most accurate structure which deals with design of multiprocessor system on chips (MPSoC). As the research advances NoC provides freedom from complex wiring and also generates opportunity for large scalability. Compared to many traditional topologies, mesh based network on chips is a widely used architecture for better scalability. With increase in diameter area of NoC there exists low latency communication among the cores. In this paper we propose a bypass router for NoC in which a single cycle data path is implemented via source terminal to destination. Proposed router is in synchrony with all existing topologies acceptance algorithms. Also a new routing algorithm is proposed in accordance with the router design. Compared with 4×4,8×8,16×16 mesh topologies with SAMRT (single-cycle multi-hop asynchronous repeated traversal) networks the area utilization is also reduced. Simulation result using Noxim and Orion 2.0 simulator displays 60% latency reduction compared with baseline routers.