ABSTRACT
This chapter surveys state-of-the-art manycore platforms. Single-core designs have traditionally been concerned with the development of techniques to efficiently extract instruction-level parallelism. The network-on-chip (NoC) holds a key role in the average performance of manycore architectures, especially when different clusters need to exchange messages. NoC traffic through a router does not interfere with the memory buses of the underlying I/O subsystem (IOS) or compute cluster, unless that router is the destination node. The compute cluster is the basic processing unit of the multi-purpose processor array (MPPA) architecture. The communication with the MPPA-256 can thus be performed in a couple of steps which can be referred to as Host-to-IOS, IOS-to-Clusters and finally Cluster-to-Cluster communication protocols. A direct memory access engine is responsible for transferring data between the shared memory and the NoC or within the shared memory.
