ABSTRACT
In this article, we have proposed a quantitative evaluation approach and an on-chip calibration architecture to evaluate the aging reliability of Integrated circuits (ICs). The on-chip calibration architecture comprises a configurable ring oscillator, an edge detection circuit, and a test and control module. The return path of the configurable ring oscillator is used for calibration to achieve precise clock cycle. The matching path is integrated with the ring oscillator to configure the time delay of the buffer path to match the key path. The edge detection circuit enables the calibration of the matching path. The test and control module are used to control the processing mode of the calibration architecture. The calibration architecture can achieve in-situ calibration of the time delay of the key path under different power supply voltages, which can be used to predict the burn-in speed of the critical path. The aging reliability evaluation process involves a fast aging reliability assessment method for the IC. We also designed an on-chip calibration architecture for real-time time delay calibration of the key path during normal circuit operation to keep track of the aging process.
