ABSTRACT
The modern era, Carbon Nano-tube Field effect transistor (CNT FET) play a significant role in circuit design for various aspects. As the demand for high-speed and energy-efficient arithmetic units develops, it becomes critical to investigate novel adder architectures. Ternary arithmetic, with its potential for increased computational density and shorter carry propagation delays, has emerged as a possible alternative to binary arithmetic. The overview of the ternary logic has discussed initial phase, the next important parameters like propagation delay, power dissipation, power delay product. Energy delay product analysis has elaborated. Further literature survey has done from fast decade on ternary logic circuits, which can work efficiently with low power consumption. Then it digs into the architectural complexities of TCLAs, focusing on the methods for ternary carry look-ahead and efficient ternary sum generation. Various optimization strategies for increasing the speed and area efficiency of TCLAs are also examined, such as hybrid carry generation schemes and transistor-level optimizations.
