ABSTRACT
To achieve transmission speeds exceeding 1 Tb/s per channel at low cost/bit, it is essential to generate electrical multi-level pulse-amplitude modulated signals (PAM-4/8) at extremely high symbol-rates (>100 GBaud) [1]. Current digital systems heavily rely on silicon-based digital-to-analog converters (DACs), which analog bandwidth typically caps around 30–40 GHz [2]. Consequently, their signal-to-noise ratio (SNR) is often sacrificed to digitally enhance their band-width. This necessitates a DAC with a high effective number of bits at half the Nyquist frequency (>3–4 typically), leading to increased footprint and power consumption of the DAC IC. Along with the silicon CMOS data converters, silicon germanium (SiGe) linear amplifiers are often used to drive the optical modulators. However, these SiGe drivers suffer from a restricted bandwidth × output swing of less than 180 GHz.Vpp [3]-[4]. As a consequence, optical transmitter frontends are either based on (i) sub-driven high-bandwidth modulators, which restrict the link reach and/or symbol-rate due to the subsequent optical SNR penalties, or (ii) low-Vpi modulators, compromising the overall bandwidth and/or footprint depending on which technology is used. Furthermore, power hungry digital signal processing (DSP) is frequently used to address various impairments, including bandwidth limitations, which significantly increases transceivers’ power consumption, the link latency, and the analog signal peak-to-average power ratio (PAPR). Higher PAPR demands higher linearity in the analog front-end, thereby affecting its power consumption. Moreover, for next-generation optical systems operating beyond 200 GBaud, severe bandwidth degradations are caused by chip-to-chip interconnections and packaging [4], requiring extra DSP for compensation.
