ABSTRACT
This chapter describes a thorough comparative study of performance evaluation, estimation of energy consumptions and area overhead of different mesh- and tree-based network-on-chip topologies have been shown with the number of intellectual property (IP) cores under the bisection width constraint. It considers two variants of mesh structure—one core and two cores connected to each router, butterfly fat tree, and mesh-of-tree network structures—and compares their performance and cost for a 32-core-based system. The simulator operates at the granularity of individual architectural components of the router. The chapter presents traffic injected by the IP cores follows self-similar distribution. It shows that modeling of self-similar traffic can be obtained by aggregating a large number of ON-OFF message sources. The chapter uses both flit size and link width equal to 32 bits for all the networks under consideration, keeping the wire dimension unchanged. The performance of an on-chip communication network is characterized by its throughput and latency.
