ABSTRACT
This chapter explains on-chip interconnects in network-on-chip design and related issues. It reviews the work of L. Benin and G. D. Michele that the impact of inductance in most on-chip interconnects is negligible and can be modelled as a distributed resistance-capacitance wire. The chapter describes the sources of different types of faults such as permanent faults, faults due to aging effect, and transient faults in deep submicron technology. It also describes the intra- and inter-router transient faults and discusses different crosstalk avoidance techniques, soft error protection techniques, and error controlling techniques. The chapter highlights a unified coding framework to address crosstalk avoidance, power minimization in bus, and error correction jointly. Depending on the transition time of the victim and aggressor nets, another ill effect of capacitive crosstalk is crosstalk double switching. Signal integrity and reliability issues in network-on-chip need to be addressed efficiently to solve the problems of transmission errors and power consumption.
