ABSTRACT
Due to metal-oxide-semiconductor field-effect transistor (MOSFET) downscaling, gate electric field increases. With the increase in electric field, an increase in chip operating temperature takes place, which is a serious reliability concern in silicon-integrated circuits. Moreover, the recent introduction of high-k gate dielectrics, metal gate materials, high-mobility channels, and new 3D device architectures has created a need for clear understanding of the reliability issues not only to negative bias temperature instability (NBTI) but also to positive bias temperature instability (PBTI). Transistors for three different types of logic are specified in the International Technology Roadmap for Semiconductors (ITRS): high performance (HP), low standby power (LSTP), and low operating power (LOP). To meet the performance and leakage current targets, key technology innovations i.e., high-k gate dielectrics and metal gate electrodes, ultra-thin body fully depleted siliconon-insulator (SOI) MOSFETs, and multiple-gate MOSFETs, have been introduced in current complementary metal-oxide-semiconductor (CMOS) processing. New generation devices are taking advantage of the properties of high-k gate dielectrics, carrier mobility enhancement techniques, and new 3D architectures. In particular, the Ni fully silicided gate electrodes, techniques for local strain introduction, such as SiGe in source/drain and contact etch stop layers (CESLs), and the 3D FinFET technology have led to different types of reliability issues. This chapter will focus on the bias temperature instability (BTI) phenomenon in relation to technology scaling. NBTI and hot-carrier injection (HCI) degradation and their impact on strainengineered MOSFETs are discussed.
