ABSTRACT
This chapter looks at the continued scaling of silicon complementary metal oxide semiconductor chips and the issues imposed on assembly and packaging requirements by the new materials set used to create these integrated circuits. Metallic interconnects are conductive traces on an integrated circuit, whose purpose is to distribute clock and other signals and to connect the power/ground to the various circuit and system functions on a chip. Finding the right dielectric material to pair with copper conductors to maximize electrical performance at the given feature-size node turned out to be more problematic than expected, though implementing copper metallization was not without its own complications. 3D interconnection of active devices is an attractive solution to the problem of high-frequency signal propagation between chips. Stacking chips physically and electrically may improve electrical performance while reducing space and volume required in a system, when compared to a set of stand-alone integrated circuits.
